1. Field of the Invention
The present invention relates to a clock signal modeling circuit, and in particular, to a negative delay circuit having a multi-locking prevention circuit.
2. Background of the Related Art
As memory device technology advances, a memory device operates at higher speeds. The internal clock signal for a memory chip is generally obtained by delaying an external clock signal for a predetermined period time. However, there is a limit for delaying the external clock signal. For example, when accessing the data of the memory device using an internal clock signal which is based on a delayed external clock signal, the access time is increased.
Therefore, the delay time between an external clock signal and an internal clock signal is reduced by using a PLL(Phase Locked Loop) or a DLL(Delay Locked Loop) or the internal clock signal is generated more rapidly than the external clock signal. The process in which the internal clock signal is more rapidly generated than the external clock signal is called a negative delay. When using the PLL or DLL, a few hundreds of clock cycles are needed for providing a locked clock signal. In addition, the PLL or DLL increases the current consumption.
The above references and/or descriptions are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.